For an increasing range of applications, low power dissipation is an integrated circuit (IC) feature that is as important as area and speed. For portable systems, low power circuits allow longer periods of operation. For ICs embedded in high performance systems, low power reduces the expense for chip cooling or increases reliability due to the low chip temperature. One disadvantage associated with a reduced supply voltage is that transistors can become more sensitive to gate delays due to perimeter variations. Furthermore, smaller geometry transistors with a smaller feature size increase the effects of geometry dependent perimeter variations. These variations act globally on the entire chip so that each device on a chip can show the same order of deviations. Worst case parameters are often chosen during design to counter the effects of global intra die variations.
The yield of low voltage digital circuits is sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Such deviations can be caused by statistical deviations of the doping concentration that lead to more pronounced delay variations for minimum transistor sizes. The path delay variations increase for smaller device dimensions and reduced supply voltages. Circuits with a number of critical paths having a low logic depth are particularly sensitive to uncorrelated gate delay variations. Scenarios for future technologies show the increased impact of uncorrelated delay variations on digital design.